Invention Grant
- Patent Title: High density split-gate memory cell
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Application No.: US15002302Application Date: 2016-01-20
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Publication No.: US10658027B2Publication Date: 2020-05-19
- Inventor: Nhan Do , Xian Liu , Vipin Tiwari , Hieu Van Tran
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L29/76
- IPC: H01L29/76 ; G11C11/419 ; G11C16/04 ; G11C16/14 ; H01L21/28 ; H01L29/423 ; H01L29/66 ; H01L29/788 ; H01L27/11521

Abstract:
A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.
Public/Granted literature
- US20160217849A1 High Density Split-Gate Memory Cell Public/Granted day:2016-07-28
Information query
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