- Patent Title: Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
-
Application No.: US15240422Application Date: 2016-08-18
-
Publication No.: US10658334B2Publication Date: 2020-05-19
- Inventor: Yu-Jen Cheng , Yu-Chih Huang , Chih-Hua Chen , Yu-Feng Chen , Hao-Yi Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/538 ; H01L25/065 ; H01L25/00 ; H01L23/00 ; H01L21/683 ; H01L25/10

Abstract:
Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings. The first openings are wider than the second openings. The method further includes forming first bumps over the redistribution structure. The first bumps have a lower portion filling the first openings. In addition, the method includes bonding a second integrated circuit die to the redistribution structure through second bumps having a lower portion filling the second openings. There is a space between the second integrated circuit die and the base layer. The method also includes forming a molding compound layer over the base layer. The molding compound layer fills the space and surrounds the first and second bumps.
Public/Granted literature
Information query
IPC分类: