公开(公告)号：US20230307392A1

公开(公告)日：2023-09-28

申请号：US17841223

申请日：2022-06-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chia-Li Lin ,  Yu-Chih Huang ,  Chen-Shien Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/94 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05564 ,  H01L2224/08147 ,  H01L2224/03462 ,  H01L2224/03845 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2224/06517 ,  H01L2924/20102 ,  H01L2224/80203 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107

摘要： In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

公开(公告)号：US11741737B2

公开(公告)日：2023-08-29

申请号：US17320639

申请日：2021-05-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hua Chen ,  Yu-Feng Chen ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Yu-Chih Huang

IPC分类号： G06V40/13 ,  G06F18/00 ,  H01L21/56

CPC分类号： G06V40/1306 ,  G06F18/00 ,  G06V40/1329 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

摘要： A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

公开(公告)号：US20210098636A1

公开(公告)日：2021-04-01

申请号：US16747503

申请日：2020-01-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chih-Hao Chang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC分类号： H01L31/0203 ,  H01L31/18 ,  H01L31/024 ,  H01L31/02

摘要： A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US12113022B2

公开(公告)日：2024-10-08

申请号：US16884035

申请日：2020-05-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Cheng Tseng ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/167 ,  H01L23/3121 ,  H01L25/0652 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2225/06548

摘要： A semiconductor package includes a lower encapsulated semiconductor device, a lower redistribution structure, an upper encapsulated semiconductor device, and an upper redistribution structure. The lower redistribution structure is disposed over and electrically connected to the lower encapsulated semiconductor device. The upper encapsulated semiconductor device is disposed over the lower encapsulated semiconductor device and includes a sensor die having a pad and a sensing region, an upper encapsulating material at least laterally encapsulating the sensor die, and an upper conductive via extending through the upper encapsulating material and connected to the lower redistribution structure. The upper redistribution structure is disposed over the upper encapsulated semiconductor device. The upper redistribution structure covers the pad of the sensor die and has an opening located on the sensing region of the sensor die.

公开(公告)号：US11842993B2

公开(公告)日：2023-12-12

申请号：US18064690

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC分类号： H01L27/01 ,  H01L21/70 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L25/10

CPC分类号： H01L27/013 ,  H01L21/705 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2225/1035 ,  H01L2225/1058

摘要： A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20230253384A1

公开(公告)日：2023-08-10

申请号：US18301555

申请日：2023-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/162 ,  H01L21/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/20 ,  H01L25/16 ,  H01L25/105 ,  H01G4/00 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08225 ,  H01L2224/16235 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/15313 ,  H01L2924/19011 ,  H01L2924/19105

摘要： A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US11631658B2

公开(公告)日：2023-04-18

申请号：US17099179

申请日：2020-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01G4/00 ,  H01L25/065

摘要： A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US20230110420A1

公开(公告)日：2023-04-13

申请号：US18064690

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC分类号： H01L27/01 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L21/70 ,  H01L23/522

摘要： A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US11309225B2

公开(公告)日：2022-04-19

申请号：US16714801

申请日：2019-12-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC分类号： H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L21/78 ,  H01L25/10 ,  H01L21/683 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

摘要： A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.

公开(公告)号：US11158555B2

公开(公告)日：2021-10-26

申请号：US15939293

申请日：2018-03-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ting-Ting Kuo ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Chih-Hsuan Tai ,  Ying-Cheng Tseng

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

摘要： A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.