Invention Grant
- Patent Title: Method (and related apparatus) that reduces cycle time for forming large field integrated circuits
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Application No.: US16190757Application Date: 2018-11-14
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Publication No.: US10665455B2Publication Date: 2020-05-26
- Inventor: Wen-Chen Lu , Ming-Chang Hsieh , Yi-Min Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/027
- IPC: H01L21/027 ; H01L21/768 ; H01L23/528 ; H01L23/31 ; H01L23/522 ; G03F7/20 ; H01L21/8234

Abstract:
In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
Public/Granted literature
- US20200126785A1 METHOD (AND RELATED APPARATUS) THAT REDUCES CYCLE TIME FOR FORMING LARGE FIELD INTEGRATED CIRCUITS Public/Granted day:2020-04-23
Information query
IPC分类: