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    METHOD (AND RELATED APPARATUS) THAT REDUCES CYCLE TIME FOR FORMING LARGE FIELD INTEGRATED CIRCUITS
    1.
    发明申请
    METHOD (AND RELATED APPARATUS) THAT REDUCES CYCLE TIME FOR FORMING LARGE FIELD INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200219721A1

    公开(公告)日：2020-07-09

    申请号：US16818013

    申请日：2020-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

    IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

    METHOD (AND RELATED APPARATUS) THAT REDUCES CYCLE TIME FOR FORMING LARGE FIELD INTEGRATED CIRCUITS
    3.
    发明申请
    METHOD (AND RELATED APPARATUS) THAT REDUCES CYCLE TIME FOR FORMING LARGE FIELD INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200126785A1

    公开(公告)日：2020-04-23

    申请号：US16190757

    申请日：2018-11-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

    IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

    OPC method with higher degree of freedom
    4.
    发明授权
    OPC method with higher degree of freedom 有权
    OPC方法具有较高的自由度

    公开(公告)号：US08972909B1

    公开(公告)日：2015-03-03

    申请号：US14038943

    申请日：2013-09-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Cheng Chang ,  Jau-Shian Liang ,  Wen-Chen Lu ,  Chin-Min Huang ,  Ming-Hui Chih ,  Cherng-Shyan Tsay ,  Chien-Wen Lai ,  Hua-Tai Lin

    IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

    CPC classification number: G03F7/70441 ,  G03F1/00 ,  G03F1/36 ,  G06F17/5072 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G21K5/00

    Abstract: The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.

    Abstract translation: 本公开涉及一种执行通过使用近似设计层提供高自由度的光学邻近校正（OPC）过程的方法。 在一些实施例中，该方法通过形成具有一个或多个原始设计形状的原始设计层的集成芯片（IC）设计来执行。 从原始设计层产生与原始设计层不同的近似设计层。 近似设计层是已经被调整以去除可能引起光学邻近校正（OPC）问题的特征的设计层。 然后在近似设计层上执行光学邻近校正（OPC）过程。 通过在近似设计层而不是原始设计层上执行OPC程序，可以提高OPC程序的特性。

    METHOD (AND RELATED APPARATUS) THAT REDUCES CYCLE TIME FOR FORMING LARGE FIELD INTEGRATED CIRCUITS
    6.
    发明申请
    METHOD (AND RELATED APPARATUS) THAT REDUCES CYCLE TIME FOR FORMING LARGE FIELD INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200211836A1

    公开(公告)日：2020-07-02

    申请号：US16818056

    申请日：2020-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

    IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

    Methods of manufacturing semiconductor device and semiconductor device
    8.
    发明授权
    Methods of manufacturing semiconductor device and semiconductor device 有权

    公开(公告)号：US11056440B2

    公开(公告)日：2021-07-06

    申请号：US16591961

    申请日：2019-10-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ying-Hua Chen ,  Feng-Jia Shiu ,  Wen-Chen Lu

    IPC: H01L23/544 ,  H01L23/522 ,  H01L27/22 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/24

    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a CMP stop layer is formed over the first ILD layer, a trench opening is formed by patterning the CMP stop layer and the first ILD layer, an underlying first process mark is formed by forming a first conductive layer in the trench opening, a lower dielectric layer is formed over the underlying first process mark, a middle dielectric layer is formed over the lower dielectric layer, an upper dielectric layer is formed over the middle dielectric layer, a planarization operation is performed on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark, and a second process mark by the lower dielectric layer is formed by removing the remaining part of the middle dielectric layer.

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