Invention Grant
- Patent Title: Method and system for coordinating baseline and secondary prefetchers
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Application No.: US15709285Application Date: 2017-09-19
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Publication No.: US10678692B2Publication Date: 2020-06-09
- Inventor: Seth H. Pugsley , Manjunath Shevgoor , Christopher B. Wilkerson
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F12/0862
- IPC: G06F12/0862 ; G06F9/30 ; G06F12/0811 ; G06F12/0806 ; G06F12/0897

Abstract:
In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.
Public/Granted literature
- US20190087341A1 METHOD AND SYSTEM FOR COORDINATING BASELINE AND SECONDARY PREFETCHERS Public/Granted day:2019-03-21
Information query
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