Invention Grant
- Patent Title: Integrated circuit package and method of fabricating the same
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Application No.: US15486306Application Date: 2017-04-13
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Publication No.: US10685896B2Publication Date: 2020-06-16
- Inventor: Zi-Jheng Liu , Hung-Jui Kuo , Yu-Hsiang Hu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/498 ; H01L23/00 ; H01L25/11 ; H01L23/544 ; H01L25/00 ; H01L21/683 ; H01L21/56 ; H01L25/10 ; H01L23/538

Abstract:
An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.
Public/Granted literature
- US20180301389A1 INTEGRATED CIRCUIT PACKAGE AND METHOD OF FABRICATING THE SAME Public/Granted day:2018-10-18
Information query
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