Invention Grant
- Patent Title: Charge loss failure mitigation
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Application No.: US16274806Application Date: 2019-02-13
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Publication No.: US10692580B2Publication Date: 2020-06-23
- Inventor: Vipul Patel
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/26 ; G11C16/10 ; G11C16/30 ; G11C16/08 ; G11C16/28 ; G11C11/56

Abstract:
Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number of memory cells of a subset of memory cells of the particular grouping of memory cells having a particular data state, and, if the number of memory cells of the subset of memory cells having the particular data state is less than a particular threshold, adjusting a voltage level of the read voltage in response to the number of memory cells of the subset of memory cells having the particular data state and reading the particular grouping of memory cells using the read voltage having the adjusted voltage level.
Public/Granted literature
- US20190206499A1 CHARGE LOSS FAILURE MITIGATION Public/Granted day:2019-07-04
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