Invention Grant
- Patent Title: Methods for manufacturing an interconnect structure for semiconductor devices
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Application No.: US16037985Application Date: 2018-07-17
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Publication No.: US10692759B2Publication Date: 2020-06-23
- Inventor: Hao Jiang , He Ren , Hao Chen , Mehul B. Naik
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/66 ; H01L21/02 ; H01L21/033 ; H01L21/311 ; H01L21/3205 ; H01L21/3213 ; C23F1/00 ; H01L49/02

Abstract:
Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.
Public/Granted literature
- US20200027782A1 METHODS FOR MANUFACTURING AN INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES Public/Granted day:2020-01-23
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