公开(公告)号：US20240321641A1

公开(公告)日：2024-09-26

申请号：US18606739

申请日：2024-03-15

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  Jong Mun Kim ,  Jonathan Qian ,  He Ren ,  Mehul Naik

IPC分类号： H01L21/822 ,  H01L21/311

CPC分类号： H01L21/8221 ,  H01L21/31116

摘要： A method includes forming a planarization layer to a position below an upper transistor device region of a base structure of an electronic device and above a lower transistor device region of the base structure. The base structure includes a plurality of features. The method further includes forming spacer material along the base structure and the planarization layer, modifying the spacer material formed along bottom trenches of the base structure to obtain modified spacer material, and forming a spacer layer by using a wet etch process to remove the modified spacer material. Modifying the spacer material formed along the bottom trenches of the base structure to obtain the modified spacer material includes performing a dry etch process targeting the spacer material formed along the bottom trenches of the base structure.

公开(公告)号：US11908696B2

公开(公告)日：2024-02-20

申请号：US17569870

申请日：2022-01-06

申请人： Applied Materials, Inc.

发明人： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC分类号： H01L21/285 ,  H01L21/768 ,  C23C14/56 ,  C23C14/14 ,  C23C14/24 ,  C23C14/06

CPC分类号： H01L21/2855 ,  C23C14/0641 ,  C23C14/14 ,  C23C14/24 ,  C23C14/56 ,  H01L21/76829 ,  H01L21/76876

摘要： A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US11205589B2

公开(公告)日：2021-12-21

申请号：US16594057

申请日：2019-10-06

申请人： APPLIED MATERIALS, INC.

发明人： He Ren ,  Hao Jiang ,  Mehul Naik ,  Srinivas D Nemani ,  Ellie Yieh

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285 ,  H01L21/67 ,  C23C14/58 ,  H01L21/3213 ,  C23C14/16

摘要： Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.

公开(公告)号：US11967527B2

公开(公告)日：2024-04-23

申请号：US17843966

申请日：2022-06-18

申请人： Applied Materials, Inc.

发明人： He Ren ,  Hao Jiang ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L23/522

CPC分类号： H01L21/76897 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7685 ,  H01L21/76892 ,  H01L23/5226

摘要： Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

公开(公告)号：US11749532B2

公开(公告)日：2023-09-05

申请号：US17307383

申请日：2021-05-04

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  Chi Lu ,  He Ren ,  Mehul Naik

IPC分类号： H01L21/3213 ,  H01L21/033 ,  H01J37/32 ,  H01L21/67 ,  H01L23/532

CPC分类号： H01L21/32136 ,  H01J37/32449 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/67069 ,  H01J37/32183 ,  H01J2237/3341 ,  H01L23/53242

摘要： Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.

公开(公告)号：US11508617B2

公开(公告)日：2022-11-22

申请号：US16662200

申请日：2019-10-24

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/203

摘要： A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

公开(公告)号：US20220328352A1

公开(公告)日：2022-10-13

申请号：US17843966

申请日：2022-06-18

申请人： Applied Materials, Inc.

发明人： He Ren ,  Hao Jiang ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L23/522

摘要： Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

公开(公告)号：US20210104434A1

公开(公告)日：2021-04-08

申请号：US16594057

申请日：2019-10-06

申请人： APPLIED MATERIALS, INC.

发明人： He Ren ,  Hao Jiang ,  Mehul Naik ,  Srinivas D. Nemani ,  Ellie Yieh

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L21/67 ,  H01L21/3213 ,  C23C14/16 ,  C23C14/58

摘要： Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.

公开(公告)号：US10692759B2

公开(公告)日：2020-06-23

申请号：US16037985

申请日：2018-07-17

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  He Ren ,  Hao Chen ,  Mehul B. Naik

IPC分类号： H01L21/768 ,  H01L21/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  C23F1/00 ,  H01L49/02

摘要： Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

公开(公告)号：US11923244B2

公开(公告)日：2024-03-05

申请号：US17193994

申请日：2021-03-05

申请人： Applied Materials, Inc.

发明人： He Ren ,  Hao Jiang ,  Shi You ,  Mehul B. Naik

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76879

摘要： Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.