Invention Grant
- Patent Title: Apparatus for correcting a parallelism between a bonding head and a stage, and a chip bonder including the same
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Application No.: US15463061Application Date: 2017-03-20
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Publication No.: US10692833B2Publication Date: 2020-06-23
- Inventor: Jae-Cheol Kim , Gil-Man Kang , Kyoung-Bok Cho , Yong-Dae Ha
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@23d77d8
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00

Abstract:
A bonding apparatus includes a detecting unit configured to determine whether a bonding head and a stage, on which a package substrate is disposed, are sufficiently parallel to each other during a bonding process, wherein the bonding head is configured to bond a semiconductor chip to the package substrate, and a correcting unit configured to adjust at least one of the bonding head or the stage based on the determination of the detecting unit during the bonding process.
Public/Granted literature
Information query
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