Invention Grant
- Patent Title: Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
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Application No.: US15827478Application Date: 2017-11-30
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Publication No.: US10692836B2Publication Date: 2020-06-23
- Inventor: Rajendra D. Pendse
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Brian M. Kaufman; Robert D. Atkins
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L25/03 ; H01L25/065 ; H01L25/00 ; H01L21/768 ; H01L23/00 ; H01L23/498

Abstract:
A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.
Public/Granted literature
- US20180096963A1 Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration Public/Granted day:2018-04-05
Information query
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