公开(公告)号：US11251154B2

公开(公告)日：2022-02-15

申请号：US16878345

申请日：2020-05-19

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L25/03 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768

Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.

公开(公告)号：US10692836B2

公开(公告)日：2020-06-23

申请号：US15827478

申请日：2017-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/56 ,  H01L25/03 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.

公开(公告)号：US10388612B2

公开(公告)日：2019-08-20

申请号：US15664734

申请日：2017-07-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

公开(公告)号：US20170330840A1

公开(公告)日：2017-11-16

申请号：US15664734

申请日：2017-07-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L23/552 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

公开(公告)号：US20160284619A1

公开(公告)日：2016-09-29

申请号：US15173332

申请日：2016-06-03

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/46 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/435 ,  H01L2224/45144 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

公开(公告)号：US20200279827A1

公开(公告)日：2020-09-03

申请号：US16878345

申请日：2020-05-19

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L25/03 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768

Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.

公开(公告)号：US20180096963A1

公开(公告)日：2018-04-05

申请号：US15827478

申请日：2017-11-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/03 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.

公开(公告)号：US09899286B2

公开(公告)日：2018-02-20

申请号：US15153433

申请日：2016-05-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L33/62

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion.

公开(公告)号：US20160260646A1

公开(公告)日：2016-09-08

申请号：US15153433

申请日：2016-05-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.