Invention Grant
- Patent Title: Apparatuses and methods for detecting a loop count in a delay-locked loop
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Application No.: US16746352Application Date: 2020-01-17
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Publication No.: US10700689B2Publication Date: 2020-06-30
- Inventor: Yasuo Satoh
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H03L7/099
- IPC: H03L7/099 ; H03L7/081 ; G11C7/10 ; H03L7/10 ; G11C11/4093 ; H03L7/089 ; G11C7/22

Abstract:
Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.
Public/Granted literature
- US20200153443A1 APPARATUSES AND METHODS FOR DETECTING A LOOP COUNT IN A DELAY-LOCKED LOOP Public/Granted day:2020-05-14
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