- Patent Title: System and method for generation of wafer inspection critical areas
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Application No.: US15394545Application Date: 2016-12-29
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Publication No.: US10706522B2Publication Date: 2020-07-07
- Inventor: Prasanti Uppaluri , Rajesh Manepalli , Ashok V. Kulkarni , Saibal Banerjee , John Kirkland
- Applicant: KLA-Tencor Corporation
- Applicant Address: US CA Milpitas
- Assignee: KLA-Tencor Corporation
- Current Assignee: KLA-Tencor Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Suiter Swantz pc llo
- Main IPC: G06T7/00
- IPC: G06T7/00 ; H01L21/66

Abstract:
A method includes receiving one or more sets of wafer data, identifying one or more primitives from one or more shapes in one or more layers in the one or more sets of wafer data, classifying each of the one or more primitives as a particular primitive type, identifying one or more primitive characteristics for each of the one or more primitives, generating a primitive database of the one or more primitives, generating one or more rules based on the primitive database, receiving one or more sets of design data, applying the one or more rules to the one or more sets of design data to identify one or more critical areas, and generating one or more wafer inspection recipes including the one or more critical areas for an inspection sub-system.
Public/Granted literature
- US20180130195A1 System and Method for Generation of Wafer Inspection Critical Areas Public/Granted day:2018-05-10
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