Invention Grant
- Patent Title: Method of fabricating integrated fan-out packages
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Application No.: US15879457Application Date: 2018-01-25
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Publication No.: US10763206B2Publication Date: 2020-09-01
- Inventor: Po-Han Wang , Hung-Jui Kuo , Yu-Hsiang Hu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/56 ; H01L21/78 ; H01L23/31 ; H01L21/768 ; H01L23/00 ; H01L21/66 ; H01L23/538 ; H01L21/683 ; H01L23/498

Abstract:
A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.
Public/Granted literature
- US20190131235A1 STACKED VIA STRUCTURE AND METHOD OF FABRICATING THE SAME Public/Granted day:2019-05-02
Information query
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