公开(公告)号：US20240194611A1

公开(公告)日：2024-06-13

申请号：US18587407

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/538 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/2885 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/24 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L23/50 ,  H01L25/0657 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/211 ,  H01L2224/24265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19102

Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

公开(公告)号：US11817352B2

公开(公告)日：2023-11-14

申请号：US17409010

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L24/09 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

公开(公告)号：US11682647B2

公开(公告)日：2023-06-20

申请号：US16836934

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Shih-Peng Tai ,  Yu-Hsiang Hu ,  I-Chia Chen

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/2101 ,  H01L2224/2105

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

公开(公告)号：US20210391304A1

公开(公告)日：2021-12-16

申请号：US17099953

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.

公开(公告)号：US20210217709A1

公开(公告)日：2021-07-15

申请号：US17215297

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L23/58 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/00 ,  H01L21/683

Abstract: A method includes encapsulating a package component in an encapsulating material, with the encapsulating material including a portion directly over the package component. The portion of the encapsulating material is patterned to form an opening revealing a conductive feature in the package component. A redistribution line extends into the opening to contact the conductive feature. An electrical connector is formed over and electrically coupling to the conductive feature.

公开(公告)号：US10998202B2

公开(公告)日：2021-05-04

申请号：US16527015

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L21/56 ,  H01L23/367 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31

Abstract: A semiconductor package includes a die and an encapsulant. The die has an active surface and an opposite backside surface. The encapsulant wraps around the die and has a recess reaching the backside surface. A span of the recess differs from a span of the backside surface and a span of the encapsulant. A manufacturing method includes at least the following steps. A blanket die attach film is spin-coated. A light exposure process is performed to the blanket die attach film. Blanket die attach film is developed to form a patterned die adhesive. A die is disposed over the patterned die adhesive with a backside surface closer to the patterned die adhesive. The patterned die adhesive is cured to affix the die. The die and the cured die adhesive are encapsulated in an encapsulant. The cured die adhesive is removed.

公开(公告)号：US10790212B2

公开(公告)日：2020-09-29

申请号：US16675227

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3105

Abstract: A method of manufacturing a package structure includes the following processes. An adhesive layer is formed on a carrier. A die is attached to the carrier through the adhesive layer. A protection layer is formed to at least cover a sidewall and a portion of a top surface of the adhesive layer on an edge of the carrier. An encapsulant is formed over the carrier to laterally encapsulate the die. A redistribution layer (RDL) structure is formed on the die and the encapsulant. A connector is formed to electrically connect to the die through the RDL structure. The carrier is released.

公开(公告)号：US10763206B2

公开(公告)日：2020-09-01

申请号：US15879457

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00 ,  H01L21/66 ,  H01L23/538 ,  H01L21/683 ,  H01L23/498

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

公开(公告)号：US20200118960A1

公开(公告)日：2020-04-16

申请号：US16714824

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/075 ,  H01L25/07 ,  H01L25/11 ,  H01L25/04 ,  H01L23/538

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die has a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

公开(公告)号：US20200083189A1

公开(公告)日：2020-03-12

申请号：US16413591

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang ,  Yung-Chi Chu ,  Hung-Chun Cho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  C09J165/00

Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.