Invention Grant
- Patent Title: ESD network comprising variable impedance discharge path
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Application No.: US15715988Application Date: 2017-09-26
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Publication No.: US10763251B2Publication Date: 2020-09-01
- Inventor: Krishna Praveen Mysore Rajagopal , James P Di Sarro , Mariano Dissegna , Lihui Wang , Ann Margaret Concannon
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H02H9/04
- IPC: H02H9/04 ; H01L27/02 ; H02H3/20 ; H01L29/808

Abstract:
A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.
Public/Granted literature
- US20190096874A1 ESD NETWORK COMPRISING VARIABLE IMPEDANCE DISCHARGE PATH Public/Granted day:2019-03-28
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