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    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    2.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT 有权

    公开(公告)号：US20210366896A1

    公开(公告)日：2021-11-25

    申请号：US17398115

    申请日：2021-08-10

    Applicant: Texas Instruments Incorporated

    Inventor： Krishna Praveen Mysore Rajagopal ,  Mariano Dissegna

    IPC: H01L27/02 ,  H01L27/06 ,  H02H9/04

    Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    3.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT 审中-公开

    公开(公告)号：US20200343239A1

    公开(公告)日：2020-10-29

    申请号：US16393850

    申请日：2019-04-24

    Applicant: Texas Instruments Incorporated

    Inventor： Krishna Praveen Mysore Rajagopal ,  Mariano Dissegna

    IPC: H01L27/02 ,  H01L27/06 ,  H02H9/04

    Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

    SELF-BIASED BIDIRECTIONAL ESD PROTECTION CIRCUIT
    4.
    发明申请
    SELF-BIASED BIDIRECTIONAL ESD PROTECTION CIRCUIT 审中-公开

    公开(公告)号：US20190109127A1

    公开(公告)日：2019-04-11

    申请号：US16199265

    申请日：2018-11-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Antonio Gallerano ,  Ann Margaret Concannon ,  Krishna Praveen Mysore Rajagopal

    IPC: H01L27/02 ,  H01L29/06 ,  H01L29/747 ,  H01L29/74

    Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.

    ESD NETWORK COMPRISING VARIABLE IMPEDANCE DISCHARGE PATH
    6.
    发明申请
    ESD NETWORK COMPRISING VARIABLE IMPEDANCE DISCHARGE PATH 审中-公开

    公开(公告)号：US20190096874A1

    公开(公告)日：2019-03-28

    申请号：US15715988

    申请日：2017-09-26

    Applicant: Texas Instruments Incorporated

    Inventor： Krishna Praveen Mysore Rajagopal ,  James P. Di Sarro ,  Mariano Dissegna ,  Lihui Wang ,  Ann Margaret Concannon

    IPC: H01L27/02 ,  H02H3/20

    Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

    Zener-triggered transistor with vertically integrated Zener diode
    10.
    发明授权
    Zener-triggered transistor with vertically integrated Zener diode 有权

    公开(公告)号：US10978443B2

    公开(公告)日：2021-04-13

    申请号：US16433632

    申请日：2019-06-06

    Applicant: Texas Instruments Incorporated

    Inventor： Akram Ali Salman ,  Jun Cai ,  Krishna Praveen Mysore Rajagopal

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8222 ,  H01L21/266 ,  H01L21/225

    Abstract: A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.

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