A memory device comprises an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor. The array comprises a plurality of stacks of conductive lines, a stack of conductive lines including a select gate line and a word line adjacent the select gate line. The device comprises an array of vertical channel lines disposed through the conductive lines to a reference line, gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors in the array of vertical channel lines and the select gate lines, charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors in the array of vertical channel lines and the word lines, and bit lines coupled to the vertical channel lines via upper ends of the vertical channel lines.