Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.