公开(公告)号：US09293202B2

公开(公告)日：2016-03-22

申请号：US14579885

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Hernan A. Castro

IPC: G11C11/00 ,  G11C13/00 ,  G11C16/06 ,  G11C7/12 ,  G11C7/10 ,  G11C13/02

CPC classification number: G11C13/0097 ,  G11C7/10 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/02 ,  G11C16/06

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US10777275B2

公开(公告)日：2020-09-15

申请号：US16143033

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Agostino Pirovano ,  Hernan A. Castro ,  Innocenzo Tortorelli ,  Andrea Redaelli

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.

公开(公告)号：US09691481B2

公开(公告)日：2017-06-27

申请号：US15261301

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Hernan A. Castro

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C7/10 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/02 ,  G11C16/06

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US09978449B2

公开(公告)日：2018-05-22

申请号：US15633454

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Hernan A. Castro

IPC: G11C11/00 ,  G11C13/00 ,  G11C13/02 ,  G11C7/10 ,  G11C16/06 ,  G11C7/12

CPC classification number: G11C13/0097 ,  G11C7/10 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/02 ,  G11C16/06

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US20170069382A1

公开(公告)日：2017-03-09

申请号：US15261301

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Hernan A. Castro

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C7/10 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/02 ,  G11C16/06

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了在相变存储器（PCM）设备中的字线路径隔离的技术和配置。 在一个实施例中，存储器件包括存储器件的存储器单元，耦合到存储器单元的位线，耦合到存储器单元的字线，耦合到位线的位线电极，字 耦合到字线的选择模块的限流电路，耦合到具有较低电位的字线电极和位线电极之一的选择模块的限流电路，所述限流电路有助于选择操作 存储单元，所述感测电路耦合到所述字线电极和具有较低电位的所述位线电极之一，所述感测电路执行所述存储单元的读取操作，以及耦合到所述存储单元的写入电路 的字线电极和具有较低电位的位线电极，写电路执行存储单元的写操作。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10535404B2

公开(公告)日：2020-01-14

申请号：US15983746

申请日：2018-05-18

Applicant: Intel Corporation

Inventor： Hernan A. Castro

IPC: G11C11/00 ,  G11C13/00 ,  G11C16/06 ,  G11C7/12 ,  G11C7/10 ,  G11C13/02

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US09123410B2

公开(公告)日：2015-09-01

申请号：US14011476

申请日：2013-08-27

Applicant: Intel Corporation

Inventor： Hernan A. Castro ,  Jeremy M. Hirst ,  Eric Carman

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/12

CPC classification number: G11C13/0004 ,  G11C8/12 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C2213/77

Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.

Abstract translation: 本公开涉及存储器控制器。 存储器控制器可以包括存储器控制器模块，该存储器控制器模块被配置为响应于存储器访问请求识别目标字线，所述存储器访问请求包括在交叉点存储器中的目标字线，所述存储器控制器模块还被配置为执行存储器访问操作 交叉点存储器的存储单元，存储单元耦合在目标字线和位线之间; 以及字线控制模块，被配置为浮动与所述目标字线相邻的至少一个相邻字线，所述浮动包括将所述至少一个相邻字线与第一电压源或第二电压源中的至少一个相分离。 在一些实施例中，浮动在存储器访问操作期间减少与目标字线相关联的有效电容。