Invention Grant
- Patent Title: Metal gate transistor with a stacked double sidewall spacer structure
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Application No.: US15710820Application Date: 2017-09-20
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Publication No.: US10777657B2Publication Date: 2020-09-15
- Inventor: Te-Chang Hsu , Chun-Chia Chen , Yao-Jhan Wang , Chun-Jen Huang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@e156528
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/49 ; H01L21/768 ; H01L21/28 ; H01L29/78 ; H01L21/8238 ; H01L29/08 ; H01L29/16 ; H01L29/24 ; H01L29/161
Abstract:
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
Public/Granted literature
- US20190058050A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2019-02-21
Information query
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