Invention Grant
- Patent Title: Delay-based residue stage
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Application No.: US16860145Application Date: 2020-04-28
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Publication No.: US10778243B2Publication Date: 2020-09-15
- Inventor: Visvesvaraya Appala Pentakota , Rishi Soundararajan , Shagun Dusad , Chirag Chandrahas Shetty
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Mark Allen Valetti; Charles A. Brill; Frank D. Cimino
- Main IPC: H03M1/38
- IPC: H03M1/38 ; H03K5/24 ; H03M1/00 ; H03K19/20 ; H03M1/12 ; H03M1/14

Abstract:
An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.
Public/Granted literature
- US20200259501A1 DELAY-BASED RESIDUE STAGE Public/Granted day:2020-08-13
Information query
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