Invention Grant
- Patent Title: Semiconductor chip including self-aligned, back-side conductive layer and method for making the same
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Application No.: US16144169Application Date: 2018-09-27
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Publication No.: US10784161B2Publication Date: 2020-09-22
- Inventor: Ingo Muri , Bernhard Goller
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2403151f
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/302 ; H01L21/321 ; H01L21/78 ; H01L23/528

Abstract:
A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.
Public/Granted literature
- US20190096758A1 Semiconductor Chip Including Self-Aligned, Back-Side Conductive Layer and Method for Making the Same Public/Granted day:2019-03-28
Information query
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