-
公开(公告)号：US20220246744A1
公开(公告)日：2022-08-04
申请号：US17590685
申请日：2022-02-01
摘要： A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.
-
公开(公告)号：US20180330981A1
公开(公告)日：2018-11-15
申请号：US16032862
申请日：2018-07-11
发明人： Roland Rupp , Hans-Joachim Schulze , Francisco Javier Santos Rodriguez , Iris Moder , Ingo Muri
IPC分类号： H01L21/762 , H01L21/265 , H01L21/306
CPC分类号： H01L21/76243 , H01L21/02005 , H01L21/26533 , H01L21/304 , H01L21/30604 , H01L21/30608 , H01L21/30625 , H01L21/324 , H01L21/7806
摘要： According to various embodiments, a method includes: providing a substrate having a first side and a second side opposite the first side; forming a buried layer in and/or over the substrate by implanting a chemical element having a greater electronegativity than the substrate into the first side of the substrate by ion implantation; and thinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.
-
3.发明申请公开(公告)号：US20180267408A1
公开(公告)日：2018-09-20
申请号：US15919989
申请日：2018-03-13
发明人： Joerg Ortner , Iris Moder , Ingo Muri
摘要： An exposure method includes projecting a reticle pattern into a first exposure field of a photoresist layer, wherein the reticle pattern includes first and second line patterns on opposite edges of the reticle pattern and wherein at least the first line pattern includes an end section through which light flux decreases outwards. The reticle pattern is further projected into a second exposure field of the photoresist layer, wherein a first tapering projection zone of the end section of the first line pattern in the second exposure field overlaps a projection area of the second line pattern in the first exposure field.
-
公开(公告)号：US10074566B2
公开(公告)日：2018-09-11
申请号：US15596961
申请日：2017-05-16
IPC分类号： H01L21/301 , H01L21/78 , H01L21/306 , H01L21/311 , H01L21/683 , H01L21/768 , H01L23/528 , H01L29/06 , H01L21/02 , H01L21/304 , H01L21/82
CPC分类号： H01L21/78 , H01L21/02013 , H01L21/304 , H01L21/3043 , H01L21/30604 , H01L21/31111 , H01L21/6835 , H01L21/76895 , H01L21/82 , H01L23/528 , H01L29/0657 , H01L29/0834 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/861 , H01L2221/68327 , H01L2221/6834
摘要： A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor wafer towards a second lateral surface of the semiconductor wafer. The method further includes filling a portion of the plurality of trenches with filler material. The method further includes thinning the semiconductor wafer from the second lateral surface of the semiconductor wafer to form a thinned semiconductor wafer. The method further includes forming a back side metallization layer structure on a plurality of semiconductor chip regions of the semiconductor wafer after thinning the semiconductor wafer. The method further includes removing a part of the filler material from the plurality of trenches after forming the back side metallization layer structure to obtain the plurality of semiconductor devices.
-
公开(公告)号：US20180144982A1
公开(公告)日：2018-05-24
申请号：US15809280
申请日：2017-11-10
发明人： Ingo Muri , Oliver Hellmund , Iris Moder , Hans-Joachim Schulze
IPC分类号： H01L21/78 , H01L21/265 , H01L21/3205 , H01L23/14
CPC分类号： H01L21/78 , H01L21/265 , H01L21/32051 , H01L23/14
摘要： A method is disclosed for use in manufacturing semiconductor dice. The method comprises providing a wafer substrate that comprises dicing areas, providing a first etch stop material outside the dicing areas, and etching the wafer substrate down to the first etch stop material. A semiconductor device chip is also disclosed. The semiconductor device chip comprises a device layer comprising a semiconductor device and a metal support layer supporting the device layer. The metal support layer provides a metal side wall protection of the device layer.
-
公开(公告)号：US20170133465A1
公开(公告)日：2017-05-11
申请号：US14936279
申请日：2015-11-09
发明人： Anton Mauder , Frank Pfirsch , Hans-Joachim Schulze , Ingo Muri , Iris Moder , Johannes Baumgartl
IPC分类号： H01L29/10 , H01L21/265 , H01L21/324 , H01L27/088 , H01L21/306 , H01L21/3205 , H01L29/78 , H01L29/66 , H01L21/304
CPC分类号： H01L29/1095 , H01L21/265 , H01L21/304 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/3205 , H01L21/324 , H01L27/088 , H01L29/0661 , H01L29/0834 , H01L29/16 , H01L29/1608 , H01L29/2003 , H01L29/417 , H01L29/45 , H01L29/66136 , H01L29/66348 , H01L29/66477 , H01L29/7397 , H01L29/78
摘要： In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.
-
7.发明授权Semiconductor arrangement including buried anodic oxide and manufacturing method 有权半导体装置包括埋置阳极氧化物和制造方法公开(公告)号：US09472395B2
公开(公告)日：2016-10-18
申请号：US14594838
申请日：2015-01-12
发明人： Hans-Joachim Schulze , Ingo Muri , Iris Moder
IPC分类号： H01L21/02 , H01L21/74 , H01L21/225
CPC分类号： H01L21/02258 , H01L21/02238 , H01L21/2252 , H01L21/74 , H01L21/78
摘要： In accordance with a method of manufacturing a semiconductor arrangement, a first trench is formed into a semiconductor body from a first side. An anodic oxide structure is formed at a bottom side of the first trench by immersing the semiconductor body in an electrolyte and applying an anodizing voltage between the semiconductor body and an electrode in contact with the electrolyte.
摘要翻译： 根据制造半导体装置的方法，从第一侧将第一沟槽形成为半导体本体。 通过将半导体本体浸入电解质中并在半导体本体和与电解质接触的电极之间施加阳极氧化电压，在第一沟槽的底侧形成阳极氧化物结构。
-
公开(公告)号：US12107130B2
公开(公告)日：2024-10-01
申请号：US17235989
申请日：2021-04-21
发明人： Ingo Muri , Johannes Konrad Baumgartl , Oliver Hellmund , Jacob Tillmann Ludwig , Iris Moder , Thomas Neidhart , Gerhard Schmidt , Hans-Joachim Schulze
IPC分类号： H01L29/36 , H01L21/02 , H01L21/223 , H01L21/225 , H01L21/265 , H01L29/167
CPC分类号： H01L29/36 , H01L21/02236 , H01L21/02381 , H01L21/2236 , H01L21/2253 , H01L21/26513 , H01L29/167
摘要： A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.
-
公开(公告)号：US11328955B2
公开(公告)日：2022-05-10
申请号：US16938206
申请日：2020-07-24
发明人： Ingo Muri , Bernhard Goller
IPC分类号： H01L21/768 , H01L21/302 , H01L21/321 , H01L21/78 , H01L23/528
摘要： A substrate wafer arrangement includes a substrate layer having a first main side and a second main side opposite the first main side, the first main side being a front-side and the second main side being a back-side, the substrate layer further having a plurality of semiconductor chips. A polymer structure arranged between the plurality of semiconductor chips extends at least from the front-side of the substrate layer to the back-side of the substrate layer and protrudes from a back-side surface of the substrate layer. The polymer structure separates a plurality of insular islands of conductive material, each insular island corresponding to a respective semiconductor chip of the plurality of semiconductor chips. Semiconductor devices produced from the substrate wafer arrangement are also described.
-
10.发明授权公开(公告)号：US10784161B2
公开(公告)日：2020-09-22
申请号：US16144169
申请日：2018-09-27
发明人： Ingo Muri , Bernhard Goller
IPC分类号： H01L21/768 , H01L21/302 , H01L21/321 , H01L21/78 , H01L23/528
摘要： A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.
-
-
-
-
-
-
-
-
-
搜索结果
50 条记录 (耗时 0.023 秒)
