Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.