Invention Grant
- Patent Title: Test structures connected with the lowest metallization levels in an interconnect structure
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Application No.: US16425387Application Date: 2019-05-29
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Publication No.: US10796973B2Publication Date: 2020-10-06
- Inventor: Mankyu Yang , Vara Govindeswara Reddy Vakada , Edward Maciejewski , Brian Greene , Atsushi Ogino , Vikrant Chauhan , Prianka Sengupta
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/66 ; G01R31/26 ; H01L23/528 ; H01L23/522

Abstract:
Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.
Public/Granted literature
- US20200152531A1 TEST STRUCTURES CONNECTED WITH THE LOWEST METALLIZATION LEVELS IN AN INTERCONNECT STRUCTURE Public/Granted day:2020-05-14
Information query
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