公开(公告)号：US20200227350A1

公开(公告)日：2020-07-16

申请号：US16248317

申请日：2019-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaladhi Mehta ,  Brian Greene ,  Daniel J. Dechene ,  Ahmed Hassan

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/76

Abstract: Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.

公开(公告)号：US20190181215A1

公开(公告)日：2019-06-13

申请号：US15834443

申请日：2017-12-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Lin Hu ,  Brian Greene

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.

公开(公告)号：US10269932B1

公开(公告)日：2019-04-23

申请号：US15874341

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ankur Arya ,  Brian Greene ,  Qun Gao ,  Christopher Nassar ,  Junsic Hong ,  Vishal Chhabra

IPC: H01L27/01 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: One illustrative method disclosed herein includes, among other things, forming a first fin having first and second opposing sidewalls and forming a first sidewall spacer positioned adjacent the first sidewall and a second sidewall spacer positioned adjacent the second sidewall, wherein the first sidewall spacer has a greater height than the second sidewall spacer. In this example, the method further includes forming epitaxial semiconductor material on the fin and above the first and second sidewall spacers.

公开(公告)号：US10796973B2

公开(公告)日：2020-10-06

申请号：US16425387

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L29/423 ,  H01L21/66 ,  G01R31/26 ,  H01L23/528 ,  H01L23/522

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

公开(公告)号：US10790204B2

公开(公告)日：2020-09-29

申请号：US16185696

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/66 ,  H01L29/772

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

公开(公告)号：US20200152531A1

公开(公告)日：2020-05-14

申请号：US16425387

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  G01R31/26

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

公开(公告)号：US20200152530A1

公开(公告)日：2020-05-14

申请号：US16185696

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L21/66 ,  H01L23/528 ,  H01L21/768

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

公开(公告)号：US10566411B2

公开(公告)日：2020-02-18

申请号：US15834443

申请日：2017-12-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Lin Hu ,  Brian Greene

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768

Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.

公开(公告)号：US09780002B1

公开(公告)日：2017-10-03

申请号：US15173766

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Brian Greene ,  Mahender Kumar ,  Daniel J. Dechene ,  Daniel Jaeger

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L21/26506 ,  H01L21/02118 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.