Invention Grant
- Patent Title: Differential work function between gate stack metals to reduce parasitic capacitance
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Application No.: US15770468Application Date: 2015-12-17
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Publication No.: US10797150B2Publication Date: 2020-10-06
- Inventor: Sean T. Ma , Willy Rachmady , Matthew V. Metz , Chandra S. Mohapatra , Gilbert Dewey , Nadia M. Rahhal-Orabi , Jack T. Kavalieros , Anand S. Murthy , Tahir Ghani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/066478 WO 20151217
- International Announcement: WO2017/105469 WO 20170622
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/49 ; H01L29/78 ; H01L29/10 ; H01L21/28 ; H01L29/205 ; H01L29/66
Abstract:
An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.
Public/Granted literature
- US20180315827A1 DIFFERENTIAL WORK FUNCTION BETWEEN GATE STACK METALS TO REDUCE PARASITIC CAPACITANCE Public/Granted day:2018-11-01
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