Invention Grant
- Patent Title: Techniques for MRAM MTJ top electrode to metal layer interface including spacer
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Application No.: US16580419Application Date: 2019-09-24
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Publication No.: US10797230B2Publication Date: 2020-10-06
- Inventor: Harry-Hak-Lay Chuang , Hung Cho Wang , Jiunyu Tsai , Sheng-Huang Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; H01L43/02 ; G11C11/16 ; H01L43/12

Abstract:
Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
Public/Granted literature
- US20200020848A1 TECHNIQUES FOR MRAM MTJ TOP ELECTRODE TO METAL LAYER INTERFACE INCLUDING SPACER Public/Granted day:2020-01-16
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