Invention Grant
- Patent Title: Via structure and methods thereof
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Application No.: US16713862Application Date: 2019-12-13
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Publication No.: US10854542B2Publication Date: 2020-12-01
- Inventor: Che-Cheng Chang , Chih-Han Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/528 ; H01L21/768 ; H01L21/311 ; H01L27/088 ; H01L21/8234 ; H01L21/288 ; H01L23/532 ; H01L21/027 ; H01L21/321 ; H01L29/06

Abstract:
A method includes providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate; forming a buffer layer over the substrate; forming a dielectric layer over the buffer layer; performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer; and performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening.
Public/Granted literature
- US20200118923A1 Via Structure and Methods Thereof Public/Granted day:2020-04-16
Information query
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