Invention Grant
- Patent Title: Method of forming FinFET structure with reduced Fin buckling
-
Application No.: US16414565Application Date: 2019-05-16
-
Publication No.: US10861969B2Publication Date: 2020-12-08
- Inventor: Wei-Jen Lai , Yen-Ming Chen , Tsung-Lin Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L27/092 ; H01L29/10 ; H01L29/49 ; H01L29/06 ; H01L21/02 ; H01L21/28 ; H01L21/762

Abstract:
The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
Public/Granted literature
- US20200020807A1 FinFET Structure and Method with Reduced Fin Buckling Public/Granted day:2020-01-16
Information query
IPC分类: