公开(公告)号：US11935795B2

公开(公告)日：2024-03-19

申请号：US17876442

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung Wang ,  Tsung-Lin Lee ,  Wen-Chih Chiang ,  Kuan-Jung Chen

IPC: H01L21/8249 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/06

CPC classification number: H01L21/8249 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/3065 ,  H01L27/0623

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

公开(公告)号：US11894381B2

公开(公告)日：2024-02-06

申请号：US16665791

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Tsung-Lin Lee ,  Chung-Ming Lin ,  Wen-Chih Chiang ,  Cheng-Hung Wang

IPC: H01L27/12 ,  H01L21/74 ,  H01L23/535

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L23/535

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

公开(公告)号：US20230088288A1

公开(公告)日：2023-03-23

申请号：US17991560

申请日：2022-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiu Liu ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Yen-Ting Chen

IPC: H01L29/51 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

公开(公告)号：US20220384606A1

公开(公告)日：2022-12-01

申请号：US17818400

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Liang-Yin Chen ,  Yi-Hsiu Liu ,  Tsung-Lin Lee ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

公开(公告)号：US11437372B2

公开(公告)日：2022-09-06

申请号：US16938580

申请日：2020-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Chieh Hsiao ,  Johnson Chen ,  Tzung-Yi Tsai ,  Tsung-Lin Lee ,  Yen-Ming Chen

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321 ,  H01L21/8234

Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.

公开(公告)号：US11411107B2

公开(公告)日：2022-08-09

申请号：US17113955

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Yen-Ming Chen ,  Tsung-Lin Lee

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/762

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20220238350A1

公开(公告)日：2022-07-28

申请号：US17717375

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Tsung-Lin Lee ,  Po-Kang Ho

IPC: H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/51 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.

公开(公告)号：US20210351277A1

公开(公告)日：2021-11-11

申请号：US16872166

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsin Yang ,  Yen-Ming Chen ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Dian-Han Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L21/764 ,  H01L21/8238 ,  G06F30/392

Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

公开(公告)号：US11088022B2

公开(公告)日：2021-08-10

申请号：US16276121

申请日：2019-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Tsung-Lin Lee ,  Yen-Ming Chen

IPC: H01L21/4763 ,  H01L21/768 ,  H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/02

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

公开(公告)号：US11031320B2

公开(公告)日：2021-06-08

申请号：US16675702

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.