公开(公告)号：US20240371930A1

公开(公告)日：2024-11-07

申请号：US18769934

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Wei-Jen Lai ,  Chien-I Kuo ,  Wei-Yuan Lu ,  Chia-Pin Lin ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

公开(公告)号：US11855207B2

公开(公告)日：2023-12-26

申请号：US17876330

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Yen-Ming Chen ,  Tsung-Lin Lee

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/4966

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20200020807A1

公开(公告)日：2020-01-16

申请号：US16414565

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Yen-Ming Chen ,  Tsung-Lin Lee

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8238

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20220367670A1

公开(公告)日：2022-11-17

申请号：US17320428

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Wei-Yuan Lu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.

公开(公告)号：US11411107B2

公开(公告)日：2022-08-09

申请号：US17113955

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Yen-Ming Chen ,  Tsung-Lin Lee

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/762

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20210119046A1

公开(公告)日：2021-04-22

申请号：US17113955

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Yen-Ming Chen ,  Tsung-Lin Lee

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/762

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US12302611B2

公开(公告)日：2025-05-13

申请号：US18521584

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lai ,  Yen-Ming Chen ,  Tsung-Lin Lee

IPC: H10D30/69 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H10D62/10 ,  H10D64/66 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20220367622A1

公开(公告)日：2022-11-17

申请号：US17530026

申请日：2021-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Wei-Jen Lai ,  Chien-I Kuo ,  Wei-Yuan Lu ,  Chia-Pin Lin ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

公开(公告)号：US12080759B2

公开(公告)日：2024-09-03

申请号：US17530026

申请日：2021-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Wei-Jen Lai ,  Chien-I Kuo ,  Wei-Yuan Lu ,  Chia-Pin Lin ,  Yee-Chia Yeo

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

公开(公告)号：US11626328B2

公开(公告)日：2023-04-11

申请号：US17328428

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Feng Yuan ,  Hung-Li Chiang ,  Wei-Jen Lai

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.