Invention Grant
- Patent Title: Scheduler for AMP architecture with closed loop performance controller using static and dynamic thread grouping
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Application No.: US15870764Application Date: 2018-01-12
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Publication No.: US10884811B2Publication Date: 2021-01-05
- Inventor: Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F9/50
- IPC: G06F9/50 ; G06F9/48 ; G06F1/3234 ; G06F1/329 ; G06F1/3296 ; G06F9/38 ; G06F9/26 ; G06F9/54 ; G06F1/20 ; G06F1/324 ; G06F1/3206 ; G06F9/30

Abstract:
Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
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