- Patent Title: Multiple-layer, self-equalizing interconnects in package substrates
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Application No.: US16326544Application Date: 2016-09-30
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Publication No.: US10886209B2Publication Date: 2021-01-05
- Inventor: Stephen Harvey Hall , Bok Eng Cheah , Chaitanya Sreerama , Jackson Chung Peng Kong
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner. P.A.
- International Application: PCT/US2016/054939 WO 20160930
- International Announcement: WO2018/063380 WO 20180405
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/66 ; H01L21/48

Abstract:
A self-equalizing interconnect in a connector is installed in a microelectronic device. The self-equalizing interconnect is formed of a plurality of electrically conductive layers under conditions to offset skin-effect losses with respect to frequency change during operation. Each successive layer is configured to with the next highest electrical conductivity and subsequent electrically conductive films gradually decrease in electrical conductivity. In an embodiment, thickness of the conductive film adjacent the reference plain is configured thinnest and subsequent films are added and are seriatim gradually thicker. The highest electrically conductive film is configured closest to a reference plane in the connector, and the lowest electrically conductive film is farthest from the reference plane.
Public/Granted literature
- US20190214336A1 MULTIPLE-LAYER, SELF-EQUALIZING INTERCONNECTS IN PACKAGE SUBSTRATES Public/Granted day:2019-07-11
Information query
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