Electrical interconnect for a flexible electronic package

    公开(公告)号:US10354957B2

    公开(公告)日:2019-07-16

    申请号:US15778379

    申请日:2015-11-25

    申请人: Intel Corporation

    摘要: An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.

    Pattern-edged metal-plane resonance-suppression

    公开(公告)号:US11277903B2

    公开(公告)日:2022-03-15

    申请号:US16368221

    申请日:2019-03-28

    申请人: Intel Corporation

    摘要: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.

    TRANSMISSION LINE DESIGN WITH ROUTING-OVER-VOID COMPENSATION

    公开(公告)号:US20190008029A1

    公开(公告)日:2019-01-03

    申请号:US16021618

    申请日:2018-06-28

    申请人: Intel Corporation

    IPC分类号: H05K1/02 H01L23/498 H01L23/64

    摘要: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.

    Routing-over-void-T-line-compensation

    公开(公告)号:US10484231B2

    公开(公告)日:2019-11-19

    申请号:US16021292

    申请日:2018-06-28

    申请人: Intel Corporation

    IPC分类号: H04L29/10 H05K1/02 H01R13/66

    摘要: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the signal conductor can include a first part routed over the major surface of a first side of the reference plane structure on a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of the reference plane structure on a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory, and a third portion connecting the first portion with the second portion, the third portion spanning the void, and having a plurality of spurs extending from a body of the third portion.

    PATTERN-EDGED METAL-PLANE RESONANCE-SUPPRESSION

    公开(公告)号:US20220304143A1

    公开(公告)日:2022-09-22

    申请号:US17694201

    申请日:2022-03-14

    申请人: Intel Corporation

    IPC分类号: H05K1/02 G05B19/4097 H05K3/02

    摘要: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.