Invention Grant
- Patent Title: Fabric die to fabric die interconnect for modularized integrated circuit devices
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Application No.: US16456647Application Date: 2019-06-28
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Publication No.: US10886218B2Publication Date: 2021-01-05
- Inventor: Chee Hak Teh , Chee Seng Leong , Lai Guan Tang , Han Wooi Lim , Hee Kong Phoon
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Fletcher Yoder, P.C.
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/498 ; H03K19/177 ; H03K19/17704

Abstract:
The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
Public/Granted literature
- US20190326210A1 Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices Public/Granted day:2019-10-24
Information query
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