公开(公告)号：US10886218B2

公开(公告)日：2021-01-05

申请号：US16456647

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H01L23/498 ,  H03K19/177 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US20230378061A1

公开(公告)日：2023-11-23

申请号：US18137405

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H03K19/17704 ,  H01L23/498

CPC classification number: H01L23/528 ,  H03K19/17704 ,  H01L23/49816

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US20240312909A1

公开(公告)日：2024-09-19

申请号：US18670390

申请日：2024-05-21

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H01L23/498 ,  H03K19/17704

CPC classification number: H01L23/528 ,  H01L23/49816 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US12009298B2

公开(公告)日：2024-06-11

申请号：US18137405

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H01L23/498 ,  H03K19/17704

CPC classification number: H01L23/528 ,  H01L23/49816 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US11670589B2

公开(公告)日：2023-06-06

申请号：US17131464

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L25/075 ,  H01L33/50 ,  H01L33/54 ,  H01L33/56 ,  H01L33/58 ,  H01L33/62 ,  F21V7/05 ,  F21V7/22 ,  H01L33/60 ,  H01L23/528 ,  H03K19/17704 ,  H01L23/498

CPC classification number: H01L23/528 ,  H01L23/49816 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US20210111116A1

公开(公告)日：2021-04-15

申请号：US17131464

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H03K19/17704 ,  H01L23/498

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.