- Patent Title: Vertical memory control circuitry located in interconnect layers
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Application No.: US16146938Application Date: 2018-09-28
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Publication No.: US10886286B2Publication Date: 2021-01-05
- Inventor: Ashish Verma Penumatcha , Daniel H. Morris , Uygar E. Avci , Ian A. Young
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H01L27/11514
- IPC: H01L27/11514 ; H01L27/11509 ; G11C11/22 ; H01L25/18 ; H01L23/532 ; H01L23/528

Abstract:
An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.
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