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    Memory array with ferroelectric elements
    4.
    发明授权
    Memory array with ferroelectric elements 有权

    公开(公告)号：US10720438B2

    公开(公告)日：2020-07-21

    申请号：US16146835

    申请日：2018-09-28

    申请人： Intel Corporation

    发明人： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC分类号： H01L27/11507 ,  H01L49/02 ,  H01L29/78 ,  H01L25/18 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00 ,  H01L23/16

    摘要： An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.

    Memory Array with Ferroelectric Elements
    5.
    发明申请
    Memory Array with Ferroelectric Elements 审中-公开

    公开(公告)号：US20200105771A1

    公开(公告)日：2020-04-02

    申请号：US16146835

    申请日：2018-09-28

    申请人： Intel Corporation

    发明人： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC分类号： H01L27/11507 ,  H01L49/02 ,  H01L29/78 ,  H01L25/18 ,  H01L25/065 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00

    摘要： An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.

    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSTOR GATE
    6.
    发明申请
    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSTOR GATE 审中-公开

    公开(公告)号：US20200075609A1

    公开(公告)日：2020-03-05

    申请号：US16114272

    申请日：2018-08-28

    申请人： Intel Corporation

    发明人： Daniel H. Morris ,  Seiyon Kim ,  Uygar E. Avci ,  Ian A. Young

    IPC分类号： H01L27/1159 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  G11C11/22

    摘要： Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

    Memory devices based on capacitors with built-in electric field
    7.
    发明授权
    Memory devices based on capacitors with built-in electric field 有权

    公开(公告)号：US11171145B2

    公开(公告)日：2021-11-09

    申请号：US16016375

    申请日：2018-06-22

    申请人： Intel Corporation

    发明人： Sou-Chi Chang ,  Uygar Avci ,  Daniel H. Morris ,  Seiyon Kim ,  Ashish V. Penumatcha ,  Ian A. Young

    IPC分类号： H01L27/115 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22

    摘要： Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

    Vertical memory control circuitry located in interconnect layers
    8.
    发明授权
    Vertical memory control circuitry located in interconnect layers 有权

    公开(公告)号：US10886286B2

    公开(公告)日：2021-01-05

    申请号：US16146938

    申请日：2018-09-28

    申请人： Intel Corporation

    发明人： Ashish Verma Penumatcha ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC分类号： H01L27/11514 ,  H01L27/11509 ,  G11C11/22 ,  H01L25/18 ,  H01L23/532 ,  H01L23/528

    摘要： An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.

    Ferroelectric based memory cell with non-volatile retention
    10.
    发明授权
    Ferroelectric based memory cell with non-volatile retention 有权

    公开(公告)号：US10573385B2

    公开(公告)日：2020-02-25

    申请号：US15567942

    申请日：2015-05-28

    申请人： Intel Corporation

    发明人： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC分类号： G11C5/02 ,  G11C14/00 ,  G11C11/22 ,  H01L27/11502

    摘要： Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.