公开(公告)号：US11610619B1

公开(公告)日：2023-03-21

申请号：US17530363

申请日：2021-11-18

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  H01L27/11507 ,  H01L27/11509

摘要： A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

公开(公告)号：US11380388B2

公开(公告)日：2022-07-05

申请号：US17140540

申请日：2021-01-04

申请人： Micron Technology, Inc.

发明人： Scott J. Derner ,  Charles L. Ingalls

IPC分类号： G11C11/24 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/4091 ,  H01L27/12 ,  H01L29/786 ,  H01L27/11507 ,  H01L27/11509

摘要： In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

公开(公告)号：US11367730B2

公开(公告)日：2022-06-21

申请号：US17008262

申请日：2020-08-31

申请人： Micron Technology, Inc.

发明人： Durai Vishak Nirmal Ramaswamy

IPC分类号： G11C16/04 ,  H01L27/11507 ,  G11C11/22 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/01 ,  H01L49/02

摘要： An example of an apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

公开(公告)号：US20210399051A1

公开(公告)日：2021-12-23

申请号：US16909109

申请日：2020-06-23

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yong-Jie WU ,  Yen-Chung HO ,  Pin-Cheng HSU ,  Mauricio MANFRINI ,  Chung-Te LIN

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11507 ,  H01L27/11509

摘要： A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.

公开(公告)号：US11201171B2

公开(公告)日：2021-12-14

申请号：US17008236

申请日：2020-08-31

申请人： KIOXIA CORPORATION

发明人： Sumiko Domae ,  Daisaburo Takashima

IPC分类号： G11C7/06 ,  H01L27/11597 ,  H01L27/11592 ,  H01L27/11509 ,  H01L29/78 ,  H01L29/66 ,  G11C7/18 ,  H01L27/11514

摘要： A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers.

公开(公告)号：US20210375886A1

公开(公告)日：2021-12-02

申请号：US17398536

申请日：2021-08-10

申请人： SK hynix Inc.

发明人： Eun Mee KWON ,  Da Som LEE

IPC分类号： H01L27/1158 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11514 ,  H01L27/11553 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/11526

摘要： 22In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

公开(公告)号：US11177389B2

公开(公告)日：2021-11-16

申请号：US16526074

申请日：2019-07-30

申请人： Micron Technology, Inc.

发明人： Antonino Rigano ,  Marcello Mariani

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L27/11592 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/108 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22 ,  G11C11/408 ,  H01L21/28 ,  H01L27/1159

摘要： Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11171146B2

公开(公告)日：2021-11-09

申请号：US16711884

申请日：2019-12-12

申请人： Micron Technology, Inc.

发明人： Robert B. Goodwin ,  Sanh D. Tang

IPC分类号： H01L27/11514 ,  H01L27/108 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11509 ,  G11C11/22

摘要： Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10991760B2

公开(公告)日：2021-04-27

申请号：US16385869

申请日：2019-04-16

申请人： SK hynix Inc.

发明人： Ji-Hoon Hong

IPC分类号： H01L27/24 ,  H01L27/11509 ,  H01L27/11507 ,  H01L27/22 ,  H01L23/528

摘要： A memory device includes first and second peripheral regions in which peripheral circuits related to data input/output are disposed, a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed, and a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed.

公开(公告)号：US10950286B2

公开(公告)日：2021-03-16

申请号：US16733160

申请日：2020-01-02

申请人： Micron Technology, Inc.

发明人： Christopher John Kawamura ,  Scott James Derner

IPC分类号： G11C5/10 ,  G11C5/06 ,  G11C11/22 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/11507 ,  H01L23/528 ,  G11C11/408 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  H01L27/11509

摘要： Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.