Invention Grant
- Patent Title: Partial reconfiguration for Network-on-Chip (NoC)
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Application No.: US16133357Application Date: 2018-09-17
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Publication No.: US10893005B2Publication Date: 2021-01-12
- Inventor: David P. Schultz , Ian A. Swarbrick , Jun Liu , Raymond Kong , Herve Alexanian
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H04L12/931
- IPC: H04L12/931 ; G06F15/78 ; H04L12/933 ; H04L12/761

Abstract:
Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.
Public/Granted literature
- US20200092230A1 PARTIAL RECONFIGURATION FOR NETWORK-ON-CHIP (NOC) Public/Granted day:2020-03-19
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