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    BI-DIRECTIONAL DYNAMIC FUNCTION EXCHANGE
    1.
    发明公开
    BI-DIRECTIONAL DYNAMIC FUNCTION EXCHANGE 审中-公开

    公开(公告)号：US20240202421A1

    公开(公告)日：2024-06-20

    申请号：US18066852

    申请日：2022-12-15

    Applicant: Xilinx, Inc.

    Inventor： Hao Yu ,  Raymond Kong

    IPC: G06F30/394 ,  G06F30/398

    CPC classification number: G06F30/394 ,  G06F30/398

    Abstract: Bi-directional dynamic function exchange (DFX) can include receiving a circuit design for a programmable integrated circuit (IC). The circuit design includes a plurality of DFX partitions coupled by a signal path. The circuit design can be placed using a first plurality of DFX modules for the plurality of DFX partitions, in part, by selecting a flip-flop of a connection block as a boundary flip-flop of the signal path for each DFX module of the plurality of DFX modules. The circuit design including the signal path can be routed through the selected flip-flops of the connection blocks using a bi-directional routing resource coupling the plurality of connection blocks. The bi-directional routing resource is used as a partition pin placement constraint (PPLOC) node for DFX.

    Method of enabling a partial reconfiguration in an integrated circuit device
    2.
    发明授权
    Method of enabling a partial reconfiguration in an integrated circuit device 有权

    公开(公告)号：US10558777B1

    公开(公告)日：2020-02-11

    申请号：US15820926

    申请日：2017-11-22

    Applicant: Xilinx, Inc.

    Inventor： Hao Yu ,  Raymond Kong

    IPC: G06F17/50

    Abstract: A method of implementing a partial reconfiguration in an integrated circuit device is described. The method comprises reading a netlist for a design of a circuit comprising a reconfigurable module; defining a first region of the integrated circuit device having the reconfigurable module; defining a second region that encompasses the first region; placing the reconfigurable module of the design in the first region, wherein the reconfigurable module comprises a partition pin of a plurality of available partition pins; selectively removing the partition pin; routing drivers and loads that are in the second region; and generating a partial bitstream for the reconfigurable module.

    HIERARCHICAL PARTIAL RECONFIGURATION FOR PROGRAMMABLE INTEGRATED CIRCUITS
    3.
    发明申请
    HIERARCHICAL PARTIAL RECONFIGURATION FOR PROGRAMMABLE INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200028511A1

    公开(公告)日：2020-01-23

    申请号：US16041602

    申请日：2018-07-20

    Applicant: Xilinx, Inc.

    Inventor： Hao Yu ,  Raymond Kong ,  Brian S. Martin ,  Jun Liu

    IPC: H03K19/177 ,  G06F17/50

    Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.

    Implementing circuit designs adapted for partial reconfiguration
    4.
    发明授权
    Implementing circuit designs adapted for partial reconfiguration 有权

    公开(公告)号：US10296699B1

    公开(公告)日：2019-05-21

    申请号：US15468021

    申请日：2017-03-23

    Applicant: Xilinx, Inc.

    Inventor： Hao Yu ,  Raymond Kong ,  Jun Liu

    IPC: G06F17/50

    Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.

    PARTIAL RECONFIGURATION FOR NETWORK-ON-CHIP (NOC)
    7.
    发明申请
    PARTIAL RECONFIGURATION FOR NETWORK-ON-CHIP (NOC) 审中-公开

    公开(公告)号：US20200092230A1

    公开(公告)日：2020-03-19

    申请号：US16133357

    申请日：2018-09-17

    Applicant: Xilinx, Inc.

    Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

    IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933

    Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

    Partial reconfiguration of integrated circuits using shell representation of platform design with extended routing region
    10.
    发明授权
    Partial reconfiguration of integrated circuits using shell representation of platform design with extended routing region 有权

    公开(公告)号：US10963613B1

    公开(公告)日：2021-03-30

    申请号：US16523973

    申请日：2019-07-26

    Applicant: Xilinx, Inc.

    Inventor： Meiwei Wu ,  Jun Liu ,  Raymond Kong

    IPC: G06F17/50 ,  G06F30/34 ,  G06F30/392

    Abstract: Partial reconfiguration of a programmable integrated circuit can include loading, using computer hardware, a platform design including a module black-box instance corresponding to a user design and marking, using the computer hardware, data of the platform design including data relating to synchronous boundary crossings between the platform design and the module black-box instance and implementation data for the platform design within an extended routing region available for routing the user design. Unmarked data can be removed from the platform design resulting in a shell circuit design. The user design can be implemented based on the shell circuit design and timing constraints corresponding to the marked data in the shell circuit design.

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