公开(公告)号：US12261603B2

公开(公告)日：2025-03-25

申请号：US18320168

申请日：2023-05-18

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17704 ,  H03K19/17736

Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.

公开(公告)号：US10963421B1

公开(公告)日：2021-03-30

申请号：US15964901

申请日：2018-04-27

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick

IPC: G06F15/78 ,  G06F12/02

Abstract: Embodiments herein describe a SoC that includes a mapper that identifies a destination ID for routing a transaction through a NoC. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC to transmit and receive data using the NoC. In one embodiment, the ingress logic blocks can include the mapper that identifies a destination ID for each transaction. In one embodiment, the mapper can receive a destination ID from the hardware element that submitted the transaction to the ingress logic block. In this case, the mapper can bypass the address map by using the provided destination ID. If a destination ID is not provided, however, the mapper can use an address provided in the transaction to identify the destination ID.

公开(公告)号：US20190303323A1

公开(公告)日：2019-10-03

申请号：US15936916

申请日：2018-03-27

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  David P. Schultz

IPC: G06F13/362 ,  G06F1/06 ,  G06F13/40

Abstract: A peripheral interconnect for configuring slave endpoint circuits, such as may be in a configurable network, in a system-on-chip (SoC) is described herein. In an example, an apparatus includes a processing system on a chip, a circuit block on the chip, and a configurable network on the chip. The processing system and the circuit block are connected to the configurable network. The configurable network includes a peripheral interconnect. The peripheral interconnect includes a root node and a plurality of switches. The root node and the plurality of switches are connected in a tree topology. First branches of the tree topology are connected to respective slave endpoint circuits of the configurable network. The slave endpoint circuits of the configurable network are programmable to configure the configurable network.

公开(公告)号：US11683038B1

公开(公告)日：2023-06-20

申请号：US17350639

申请日：2021-06-17

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/17712

Abstract: A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.

公开(公告)号：US10673439B1

公开(公告)日：2020-06-02

申请号：US16367108

申请日：2019-03-27

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.

公开(公告)号：US20200026684A1

公开(公告)日：2020-01-23

申请号：US16041473

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Sagheer Ahmad ,  Ygal Arbel ,  Dinesh D. Gaitonde

IPC: G06F15/78 ,  H04L12/24 ,  H04L12/933

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

公开(公告)号：US10346346B1

公开(公告)日：2019-07-09

申请号：US15851449

申请日：2017-12-21

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F15/78 ,  G06F11/10 ,  G06F13/16 ,  G11C29/52

Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

公开(公告)号：US11063594B1

公开(公告)日：2021-07-13

申请号：US16872009

申请日：2020-05-11

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

Abstract: An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.

公开(公告)号：US10824505B1

公开(公告)日：2020-11-03

申请号：US16106691

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Nishit Patel

IPC: G06F11/10 ,  G06F13/40 ,  G06F13/16 ,  G11C29/52

Abstract: An example multi-master system in a system-on-chip (SoC) includes a plurality of master circuits, an error-correcting code (ECC) proxy bridge comprising hardened circuitry in the SoC, a local interconnect configured to couple the plurality of master circuits to the ECC proxy bridge, a memory not having ECC support, and a system interconnect configured to couple the ECC proxy bridge to the memory. The ECC proxy bridge is configured to establish an ECC proxy region in the memory and, for each write transaction from the plurality of master circuits that targets the ECC proxy region, calculate and insert ECC bytes into the respective write transaction.

公开(公告)号：US10680615B1

公开(公告)日：2020-06-09

申请号：US16367073

申请日：2019-03-27

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Nagendra Donepudi

IPC: H03K19/177 ,  H03K19/17728 ,  H03K19/17756 ,  H03K19/17736 ,  H03K19/1776

Abstract: A circuit for configuring function blocks of an integrated circuit device is described. The circuit comprises a processing system; a peripheral interface bus coupled to the processing system; and a function block coupled to the peripheral interface bus, the function block having programming registers and a function block core; wherein the programming registers store data determining a functionality of the function block core and comprise programming control registers enabling a configuration of the function block core using the data. A method of configuring function blocks of an integrated circuit device is also described.