公开(公告)号：US12273106B2

公开(公告)日：2025-04-08

申请号：US18073288

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Richard W. Swanson

IPC: H03K19/018 ,  G06F13/42 ,  H03K19/0185 ,  H03K19/17736 ,  H03K21/02

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

公开(公告)号：US20190303323A1

公开(公告)日：2019-10-03

申请号：US15936916

申请日：2018-03-27

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  David P. Schultz

IPC: G06F13/362 ,  G06F1/06 ,  G06F13/40

Abstract: A peripheral interconnect for configuring slave endpoint circuits, such as may be in a configurable network, in a system-on-chip (SoC) is described herein. In an example, an apparatus includes a processing system on a chip, a circuit block on the chip, and a configurable network on the chip. The processing system and the circuit block are connected to the configurable network. The configurable network includes a peripheral interconnect. The peripheral interconnect includes a root node and a plurality of switches. The root node and the plurality of switches are connected in a tree topology. First branches of the tree topology are connected to respective slave endpoint circuits of the configurable network. The slave endpoint circuits of the configurable network are programmable to configure the configurable network.

公开(公告)号：US20210081215A1

公开(公告)日：2021-03-18

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

公开(公告)号：US10680615B1

公开(公告)日：2020-06-09

申请号：US16367073

申请日：2019-03-27

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Nagendra Donepudi

IPC: H03K19/177 ,  H03K19/17728 ,  H03K19/17756 ,  H03K19/17736 ,  H03K19/1776

Abstract: A circuit for configuring function blocks of an integrated circuit device is described. The circuit comprises a processing system; a peripheral interface bus coupled to the processing system; and a function block coupled to the peripheral interface bus, the function block having programming registers and a function block core; wherein the programming registers store data determining a functionality of the function block core and comprise programming control registers enabling a configuration of the function block core using the data. A method of configuring function blocks of an integrated circuit device is also described.

公开(公告)号：US11386009B2

公开(公告)日：2022-07-12

申请号：US16670570

申请日：2019-10-31

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Weiguang Lu ,  Karthy Rajasekharan ,  Shidong Zhou ,  Michael Tsivyan ,  Jing Jing Chen ,  Sourabh Goyal

IPC: G06F12/0855 ,  G06F9/30 ,  G06F12/06 ,  G06F12/0895 ,  G06F13/16

Abstract: An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.

公开(公告)号：US10824786B1

公开(公告)日：2020-11-03

申请号：US15285786

申请日：2016-10-05

Applicant: Xilinx, Inc.

Inventor： Jun Liu ,  Hao Yu ,  Raymond Kong ,  David P. Schultz

IPC: G06F17/50 ,  G06F30/394 ,  G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/347

Abstract: Method, apparatus and computer-readable medium for providing a partial reconfiguration of a reconfigurable module are described. In one example, a method reads a netlist for a design of a circuit comprising a reconfigurable module and sets the reconfigurable module to a first region. The method then generates a second region that encompasses the first region and places the design with the first region. The method routes the design with the second region and generates a partial bitstream for the reconfigurable module.

公开(公告)号：US20200241770A1

公开(公告)日：2020-07-30

申请号：US16262420

申请日：2019-01-30

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  David P. Schultz ,  Weiguang Lu ,  Michelle Zeng

IPC: G06F3/06

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

公开(公告)号：US20200092230A1

公开(公告)日：2020-03-19

申请号：US16133357

申请日：2018-09-17

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933

Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

公开(公告)号：US10305511B1

公开(公告)日：2019-05-28

申请号：US15990151

申请日：2018-05-25

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Weiguang Lu ,  Priyanka Agrawal ,  Jun Liu ,  Sourabh Goyal ,  David Robinson

IPC: H03M7/46 ,  G06F17/50

Abstract: Decompressing a data set includes inputting data units to a decompression circuit and comparing each input data unit to a run value and to a substitute value. In response to the data unit being not equal to the run value or the substitute value, the decompression circuit outputs the value of the input data unit; in response to the input data unit having the run value and a succeeding data unit having a value N not equal to zero or one, the decompression circuit outputs multiple data units having the run value based on the value N; in response to input data unit having the substitute value, the decompression circuit outputs one data unit having the run value; and in response to one input data unit having the run value and a succeeding data unit equal to zero or one, the decompression circuit outputs one data unit of the substitute value.

公开(公告)号：US12130769B2

公开(公告)日：2024-10-29

申请号：US18073327

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Richard W. Swanson

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F2213/0016

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.