Invention Grant
- Patent Title: Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor
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Application No.: US16364725Application Date: 2019-03-26
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Publication No.: US10896141B2Publication Date: 2021-01-19
- Inventor: Jeffrey J. Cook , Jonathan D. Pearce , Srikanth T. Srinivasan , Rishiraj A. Bheda , David B. Sheffield , Abhijit Davare , Anton Alexandrovich Sorokin
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F9/38 ; H04L9/06 ; G06F12/0815
Abstract:
In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.
Public/Granted literature
- US20200310992A1 Gather-Scatter Cache Architecture For Single Program Multiple Data (SPMD) Processor Public/Granted day:2020-10-01
Information query
