A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input signal, a first current terminal, and a second current terminal coupled to the control terminal of the second transistor and the second current terminal of the third transistor; a seventh transistor having a control terminal coupled to the control terminal of the second transistor, a first current terminal coupled to a second voltage supply, and a second current terminal coupled to the first current terminal of the fifth transistor; an eighth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second voltage supply, and a second current terminal coupled to the first current terminal of the sixth transistor; a ninth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the second current terminal of the first transistor, and a second current terminal coupled to the second current terminal of the second transistor and the second current terminal of the fifth transistor; and a tenth transistor having a control terminal coupled to the second input signal, a first current terminal coupled to the second terminal of the fourth transistor, and a second current terminal coupled to the second current terminal of the third transistor.