Invention Grant
- Patent Title: Low power device for high-speed time-interleaved sampling
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Application No.: US16683854Application Date: 2019-11-14
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Publication No.: US10911060B1Publication Date: 2021-02-02
- Inventor: Pedro W. Neto , Ronan Casey , Declan Carey
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H03M1/00
- IPC: H03M1/00 ; H03M1/46 ; G11C27/02 ; H03M1/06 ; H03M1/16

Abstract:
Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an ith sampling layer of circuits of the N sampling layers of circuits may include: (a) Xi buffers configured to receive an analog signal, Xi≥1, and, (b) Yi track-and-hold circuits, each track-and-hold circuit of the Yi track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Yi≥1, at least one buffer of the Xi buffers may include an integrating buffer, N≥i≥1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.
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